1. Field of the Invention
This invention relates to computer systems and, more particularly, to burst modes used in DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
DRAM (Dynamic Random Access Memory) devices often include a mode register. A value stored in the DRAM device's mode register controls the burst length of that DRAM device. Typically, the mode register value is initialized to identify a particular burst length during initialization. A memory controller may update the value stored in the register to change the burst length setting. However, modifying the burst length setting may be a time consuming process. For example, to program the mode register, a memory controller may wait until all DRAM accesses have completed and then issue a load mode register command by activating certain command signals (e.g., /CS (Chip Select), /RAS (Row Address Strobe), /CAS (Column Address Strobe), and /WE (Write Enable)) while placing the proper op-code onto certain pins (e.g., the address and BA0 pins). After issuing the load mode register command, the memory controller may have to wait a certain number of cycles before initiating new DRAM accesses. Accordingly, changing the burst length setting in this manner may impose an undesirable performance penalty on pending accesses.
A memory controller may receive access requests that have different burst lengths. For example, AGP (Advanced Graphics Port) transactions may involve 32 byte blocks, while processor transactions may involve 64 byte blocks. In some DRAM devices, thirty-two byte block accesses may be satisfied in four bursts, while 64 byte blocks may be satisfied in eight bursts. Since the DRAM burst length is fixed by the value stored in the mode register, either bandwidth will be wasted (if burst length is set to eight and 32 byte block transactions are being performed) or the memory controller will have to reissue commands (if burst length is set to four and 64 byte block transactions are being performed) for transactions having a particular length. However, it may be even more inefficient to change the burst length in burst mode register in order to handle transactions of a particular burst length. Thus, it is desirable to be able to dynamically change the burst length on a per-access basis without having to update the mode register.
Currently, data masking techniques exist to allow a memory device to mask certain data during write accesses so that data of a burst length less than the burst length setting in the mode register is actually written to the memory device. However, these data masking techniques do not support read accesses of different burst lengths, nor do they support accesses having burst lengths greater than that specified in the mode register. Additionally, these data masking techniques often specify which data to mask by using additional pins on the memory device, which may be undesirable in some contexts.